\prog:16F870.asi|010301 Définitions des bits des registres et registres suppl 
\const;Mémoires|
DebVar	= 16'20	; Début des variables
FinVar	= 16'7F	; Fin 1ere banque
FinProg	= 16'7FF	; 2K 
; La 2e zone en Bank1 va de 16'A0 (20) à 16'BF (1F)
; Les adresses 16'70-7F sont identiques dans les 2 banques

\const;Registres|Adresses et bits des registres
;PortA	= 5	; Connu de l'assembleur
;TrisA	= 5	; En Bank1
;PortB	= 6
;TrisB	= 6	; En Bank1
PortC	= 7	; Assembleur? 
;TMR0	= 1
;FSR	= 4
;PCL	= 2
;PCLATH	= 16'0A
; utiliser aussi PortC en bank1 a la place de TrisC en attendant l'assembleur

\b;Status, F| 16'03 toutes les banks
; Connus de l'assembleur, ne pas utiliser F
	C	= 0
	D	= 1
	DC	= 1
	Z	= 2
	PD	= 3
	TO	= 4
	RP0	= 5	; bank select
	RP1	= 6
	IRP	= 7
\b;Option| 16'01 bank1 / 16'81 (initialisé avec des 1 partout)
; Connu de l'assembleur Move W,Option agit directement
	PS0	= 0	; 000 divide per 2 on TMR0 
	PS1	= 1
	PS2	= 2
	PSA	= 3
	TOSE	= 4
	TOCS	= 5
	IntEdg	= 6
	RBPU	= 7	; = 0 pull-up actives
\b;IntCon| 16'0B toutes les banks
; Connu de l'assembleur
	RBIF	= 0
	INTF	= 1
	TOIF	= 2
	RBIE	= 3
	INTE	= 4
	TOIE	= 5
	PEIE	= 6
	GIE	= 7
\b;EECon1| 16'18C (initialisé à zéro)
EECon1	= 16'0C ; bank 3 
	RD	= 0
	WR	= 1
	WREN	= 2
	WRERR	= 3
	EEPGD	= 7
EECon2	= 16'0D ; bank 3
\b;EEAdr EEData 16 bits|  bank 2
EEADR	= 16'0D  ; bank 2
EEADRH	= 16'0F  ; bank 2
EEDATA	= 16'0C  ; bank 2
EEDATH	= 16'0E  ; bank 2

\b;PIE1| 16'8C bank 1
PIE1	= 16'0C  ; bank 1
	TMR1IE	= 0
	TMR2IE	= 1
	CCP1IE	= 2
	SSPIE	= 3
	TXIE	= 4
	RCIE	= 5
	ADIE	= 6
	PSPIE	= 7	; pas sur 28p
\b;PIR1| 16'0C
PIR1	= 16'0C
	TMR1IF	= 0
	TMR2IF	= 1
	CCP1IF	= 2
	SSPIF	= 3
	TXIF	= 4
	RCIF	= 5
	ADIF	= 6
	PSPIF	= 7	; pas sur 28p
\b;PIE2| 16'8D
PIE2	= 16'0D  ; bank 1
	EEIE	= 0
\b;PIR2| 16'0D 
PIE2	= 16'0D
	EEIF	= 0
\b;PCON| 16'8E  bank 1
PCON	= 16'0E  ; bank 1
	BOR	= 0
	POR	= 1

\b;ADCON0| 16'1F
ADCON0	= 16'1F
	ADON	= 0
	GO	= 2
	CHS0	= 3
	CHS1	= 4
	CHS2	= 5
	ADCS0	= 6
	ADCS1	= 7
\b;ADCON1| 16'9F
ADCON1	= 16'1F  ; bank 1
	PCFG0	= 0
	PCFG1	= 1
	PCFG2	= 2
	PCFG3	= 3
	ADFM	= 7
\b;ADRESH/L| 
ADRESH	= 16'1E
ADRESL	= 16'1E ; bank 1 (16'9E)

\b;TXSTA| 16'98
TXSTA	= 16'18 ; bank 1
	TX9D	= 0
	TRMT	= 1
	BRGH	= 2
	SYNC	= 4
	TXEN	= 5
	TX9	= 6
	CSRC	= 7
\b;RCSTA| 16'18 
RCSTA	= 16'18
	RX9D	= 0
	OERR	= 1
	FERR	= 2
	ADDEN	= 3
	CREN	= 4
	SREN	= 5
	RX9	= 6
	SPEN	= 7
\b;SPBRG| 16'99
SPBRG	= 16'19  ; bank 1
\b;Tx/Rx Reg
TXREG	= 16'19
RCREG	= 16'1A

\b;T1CON| 16'10
T1CON	= 16'10
	TMR1ON	= 0
	TMR1CS	= 1
	T1SYNC	= 2
	T1OSCEN	= 3
	T1CKPS0	= 4
	T1CKPS1	= 5
\b;TMRx 16-bit reg
TMR1L	= 16'0E
TMR1H	= 16'0F

\b;T2CON| 16'12
T2CON	= 16'12
	T2CKPS0	= 0
	T2CKPS1	= 1
	TMR2ON	= 2
	TOUTPS0	= 3
	TOUTPS1	= 4
	TOUTPS2	= 5
	TOUTPS3	= 6
TMR2	= 16'11
PR2	= 16'12  ; 16'92 bank2

\b;CCPR 16-bit reg
CCPR1L	= 16'15
CCPR1H	= 16'16
\b;CCP1CON| 16'17
CCP1CON	= 16'17
	CCP1M0	= 0
	CCP1M1	= 1
	CCP1M2	= 2
	CCP1M3	= 3
	CCP1Y	= 4
	CCP1X	= 5

.End